1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more specifically to a method for forming a storage node in a semiconductor memory such as a DRAM (dynamic random access memory), having such a structure that a storage capacitor is formed over a bit line.
2. Description of Related Art
In a DRAM having each one memory cell constituted of one MOS transistor (metal-oxide-semiconductor field effect transistor) and one capacitor connected to the MOS transistor, with increase of an integration density, an occupying area of each memory cell in a plan view is decreasing. However, in order to ensure a property of resisting against a soft error caused by noise electric charges generated by .alpha.-ray, each DRAM memory cell requires the associated capacitor to have a capacitance of not smaller than a certain constant value. Therefore, how a necessary amount of storage capacitance is obtained in an occupying area limited in a plan view, has become a very important technical problem. Under a recent inclination for solving the above mentioned technical problem, a three-dimensional structure has been proposed to provide a stacked capacitor over a bit line, and to increase a height of a storage node electrode constituting a lower plate of the stacked capacitor, so that a side surface area of the storage node electrode becomes large.
The structure of this stacked storage capacitor formed over the bit line is called a COB structure ("capacitor over bit-line" structure).
Now, a prior art process for forming this COB structure DRAM memory cell will be described with reference to FIGS. 1A to 1E, 2A and 2B, and 3A and 3B. FIGS. 1A to 1E are diagrammatic sectional views, taken along the line 1--1 in FIGS. 2A and 2B, of a portion of a DRAM for illustrating the prior art process for forming the COB structure DRAM memory cell. FIG. 2A is a plan view of a DRAM illustrating a portion under the bit line, and FIG. 2B is a plan view of a DRAM illustrating a positional relation between a storage node electrode, a bit line, a node contact hole and a bit contact hole. FIGS. 3A and 3B are diagrammatic sectional views of a portion of a completed DRAM, taken along the line 1--1 and along the line 2--2 in FIGS. 2A and 2B, respectively.
First, as shown in FIG. 1A, on a P-type silicon substrate 301, a field oxide film 302 is formed to confine a plurality of device formation regions, in which a gate oxide film 303 is formed to cover a surface of the P-type silicon substrate 301. These device formation regions are of a T-shape in a plan view as can be seen from FIG. 2A, and regularly arranged on a principal surface of the P-type silicon substrate 301, as shown in FIG. 2A. A plurality of word lines 304 which also function as a gate electrode, are formed to extend over the gate oxide film 303 and the field oxide film 302, and thereafter, in a surface region of the P-type silicon substrate 301 within each device formation region, N.sup.+ source/drain diffused regions 305A and 305B are formed in self alignment with the word line 304.
Then, as shown in FIG. 1B, a first interlayer insulator film 306 is formed to cover the whole surface. This interlayer insulator film 306 is formed of for example silicon oxide. A bit contact hole 307 is formed to penetrate through the interlayer insulator film 306 to reach the N.sup.+ source/drain diffused region 305A, as shown in FIG. 1B and FIG. 2A.
Furthermore, as shown in FIG. 2A, a bit line 308 is formed to cover the interlayer insulator film 306 and to fill the bit contact hole 307, so that the bit line 308 is electrically connected through the bit contact hole 307 to the N.sup.+ source/drain diffused region 305A.
Succeedingly, a second interlayer insulator film 309 is formed to cover the whole surface, as shown in FIG. 1C. This interlayer insulator film 309 is also formed of for example silicon oxide. In addition, a node contact hole 310 is formed to penetrate through the interlayer insulator films 309 and 30C to reach the N.sup.+ source/drain diffused region 305B, as shown in FIG. 1C and FIG. 2A.
Thereafter, a non-doped polysilicon film (not shown) having a desired thickness is formed to cover the whole surface, by a LPCVD (low pressure chemical vapor deposition) process using monosilane (SiH.sub.4) as a raw material under a growth temperature of 600.degree. C. to 650.degree. C. and a pressure of 13 Pa to 130 Pa. In addition, a thermal diffusion is conducted in a phosphorus oxychloride (POCl.sub.3) atmosphere at a temperature of 800.degree. C. to 900.degree. C., so that the non-doped polysilicon film is converted to N.sup.+ polysilicon film 331, as shown in FIG. 1D.
Succeedingly, the N.sup.+ polysilicon film 331 is patterned by an anisotropic dry etching using a photoresist film pattern (not shown) as a mask, to form a storage node electrode 311 formed of N.sup.+ polysilicon film, as shown in FIG. 1E and FIG. 2B.
Thereafter, the photoresist film pattern (not shown) is removed, and a capacitor dielectric film 312 and a cell plate electrode 313 are formed, as shown in FIG. 2B and FIGS. 3A and 3B. Thus, a COB structure DRAM memory cell is completed.
In the above mentioned prior art process for forming the COB structure DRAM memory cell, when the N.sup.+ polysilicon film 331 is patterned by the anisotropic dry etching to form a storage node electrode 311, a problem occurs in connection with a shape. Namely, as shown in FIG. 1E and FIGS. 3A and 3B, a notch 351 occurs in the storage node electrode 311 in a location where a side surface of the storage node electrode 311 is in contact with the interlayer insulator film 309. This notch 351 weakens a mechanical strength of the storage node electrode 311, so that, for example, in a washing step conducted after the formation of the storage node electrode 311, the storage node electrode 311 is apt to be easily lost. This lowers a production yield of the DRAM.